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1 10a synchronous buck regulator with integrated power mosfets that requires no compensation isl95210 the isl95210 single-output integrated mosfet regulator provides a precision voltage regulation system for point-of-load applications. it implements a 2- bit dac reference with tri-state inputs for selecting a variety of regulator output voltages. additionally, an external resistor divider or digital voltage margining may be used to accurately set the output voltage to a value other than the pre-selected dac voltages. an additional tri-state input pin is used to set the frequency to three pre-selected values with no need for external components. the isl95210 implements a modified version of intersil?s previous high performance r 3 ? modulator topology in the new r 4 ? modulator. this modulation scheme provides improved transient performance, while also including key performance updates that remove the need for loop compensation and produce highly accurate switchin g frequencies. these updates, along with an integrated digital feature set, allow for a high-performance regulator that is highly compact and needs few external components. protection features of this integrated regulator ic include a set of sophisticated overvoltage, undervoltage, overcurrent and thermal protections. combined, these features provide advanced protection for the load and power system. related literature ?see an1485 , ?isl95210 10a integrated fet regulator evaluation board setup procedure? features ? true 10a solution up to + 90c ambient with no air flow ? excellent efficiency - 95% peak - 87% at 800khz, 10a and 1.05v out ? best in class mosfet r ds(on) - 15m high-side -4m low-side ? 0.6% output voltage accuracy over-temperature ? intersil?s r 4 ? modulator technology - optimal transient response - no compensation required ? full digital feature set for minimal component count ? dac output voltage control with margining ? 32 lead, 6mmx4mm qfn package applications ? notebook computers -v ddq for ddr1/2/3 - chipset voltages ?mxm graphics card modules ? point of load applications ? general purpose applications isl95210 pg_out l out c out vin pvcc en pg_in vsel0 vsel1 mpct msel fccm fset pgnd agnd vcc vout phase +3.3v to +5v +1.2v 420nh 10f 220f 1f (kelvin) (kelvin) t-pad c in +5v figure 1. isl95210 typical 800khz application 0 2 4 6 8 10 12 85 90 95 100 105 110 115 120 125 isl95210 thermal performance ambient temperature (c) 200 lfm 100 lfm 300 lfm maximum continuous air flow output current (a) 0 lfm figure 2. key performance curve june 2, 2011 fn6938.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl95210 2 fn6938.2 june 2, 2011 functional block diagram dac and margin logic soft-start por bandgap r4 modulator frequency control pgood monitor dead-time control & adaptive shoot- through protection undervoltage overvoltage protection pg_in pg_out pgnd phase vin vout fset thermal monitor & protection overcurrent protection vsel0 vsel1 msel mpct vcc en fccm agnd pvcc pvcc vcc 10 ?
isl95210 3 fn6938.2 june 2, 2011 pin configuration isl95210 (32 ld qfn) top view 1 2 34 5 6 78 910 27 26 25 24 23 22 21 20 19 18 16 15 14 13 12 11 28 29 30 31 32 17 msel mpct vcc vout agnd vsel0 vsel1 pg_out pg_in pgnd pgnd pgnd pgnd pgnd vin vin dnc pgnd pgnd pvcc pvcc vin fccm fset en phase phase phase phase phase phase phase pgnd functional pin descriptions pin name function thermal pad pgnd power ground. this thermal pad provides a return path for power stage and switching currents as well as a therma l path for removing heat from the ic into the board. place thermal vias in the pad to the pgnd plane. 1 fccm logic input for operating mode selection. connect this pin to vcc for ccm regulation only. connect this pin to agnd to all ow discontinuous conduction mode for lig ht-load efficiency. float this pin for audio mode light-load switching. 2 fset tri-state digital input for programmin g the regulator switching frequency. pull th is pin to vcc for 800khz switching. pull this pin to gnd for 400khz switching. leave th is pin floating for 533khz switching. 3 en logic input for enabling and disabling output voltage regulati on. pull this pin to vcc to begin regulation. pull this pin to agnd to disable regulation. 4, 5, 6, 7, 8, 9, 10 phase power stage switching node for output voltage regu lation. connect to the output inductor. all phase pins must be shorted on the printed circuit board. 11 dnc no connect. this pin must be left floating under all conditions. 12, 13, 19, 20, 21, 22, 23 pgnd power ground. this pin provides a return path fo r power stage and switching currents. all pgnd pins must be shorted on the printed circuit board. 14, 15 pvcc power input for the integrated mosfet gate drivers. connect to a +5v supply. both pvcc pins must be shorted on the printed circuit board. 16, 17, 18 vin power input for buck regulation stage. bypass to pg nd with one 10f or 22f ceramic capacitor. connect to a +3.3v to +5v supply. all vin pins must be shorted on the printed circuit board. 24 pg_in input voltage for the power-good cmos output. co nnect this pin to the desired pgood output high level. 25 pg_out active cmos output for power-good indication. high state is indicated when the output voltage is in regulation, and out put is logic low otherwise. logic high level is set by the voltage on the pg_in pin. 26 vsel1 dac logic msb input. used to program preset output voltages of 0.60v, 0.75v, 0.90v, 1.00v, 1.05v, 1.10v, 1.20v, 1.50v, and 1.80v. 27 vsel0 dac logic lsb input. used to program preset output voltages of 0.60v, 0.75v, 0.90v, 1.00v, 1.05v, 1.10v, 1.20v, 1.50v, and 1.80v. 28 agnd ground reference for analog signals. connect this pin to the ground plane. 29 vout sense point for output voltage re gulation and output soft-discharge. co nnect to the desired regulation point.
isl95210 4 fn6938.2 june 2, 2011 30 vcc analog power supply input. used for bias and precision references. place a high frequency ceramic capacitor (0.1f to 1f) to agnd. internally connected to pvcc through a 10 resistor. 31 mpct 3-state logic input for programming the amount of output voltage ma rgining as controlled by the msel pin. pull the pin to gnd for 15% margining, to vcc for 20% marg ining, and float the pin for 10% margining. 32 msel digital input for control of output voltage margining. pull this pin to vcc to margin the output voltage to the high valu e. leave this pin floating to margin the output voltage low. pull this pin to agnd to regulate the nominally programmed output voltage value. the margin amount is dictated by the mpct pin. functional pin descriptions (continued) pin name function ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # isl95210hrz 95210 hrz -10 to +100 32 ld 6x4 qfn l32.6x4b isl95210irz 95210 irz -40 to +100 32 ld 6x4 qfn l32.6x4b ISL95210EVAL1Z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs complian t and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures th at meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level (msl), please see device information page for isl95210 . for more information on msl please see techbrief tb363 .
isl95210 5 fn6938.2 june 2, 2011 absolute maximum rating s thermal information all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v recommended operating conditions vcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5v 10% pvcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5v 10% vin supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.3v to +5v 10% junction temperature (isl95210hrz) . . . . . . . . . . . . . . .-10c to +125c junction temperature (isl95210irz) . . . . . . . . . . . . . . . .-40c to +125c thermal resistance (typical) ja (c/w) jc (c/w) 32 ld qfn package (notes 4, 5) . . . . . . . . 40 4 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions , unless otherwise specified. boldface limits apply over the operating temperature range (-10c to +100c for isl95210hrz; -40c to +100c for isl95210irz). parameter test conditions min (note 7) typ max (note 7) units bias supplies shutdown supply current [pvcc] en = low, vin = pvcc = high 0.4 10 a switching supply current [pvcc] en = hi gh, vcc = high, fset = gnd(400khz), fccm = high 7.2 ma en = high, vcc = high, fset = float (533khz), fccm = high 8.9 ma en = high, vcc = high, fset = high (800khz), fccm = high 12.2 ma standby supply current [pvcc] en = high, vcc = high, fccm = low, i out = 0a 1.9 2.7 ma vcc por (power-on reset) threshold vcc rising 4.25 4.50 v vcc falling 4.00 4.25 v pwm modulator oscillator frequency accuracy, f sw (isl95210hrz) fset=gnd(400khz)/float(533khz)/vcc (800khz) t a = +25c -5 5 % fset = gnd(400khz)/float(533khz)/vcc (800khz), -10c to +100c -10 10 % oscillator frequency accuracy, f sw (isl95210irz) fset = gnd(400khz)/float(533khz)/vcc (800khz) -40c to +100c -15 15 % control thresholds en rising threshold 2.0 v en falling threshold 1.0 v fccm, mpct, msel, fset, vsel_ input low threshold 1.20 1.50 1.80 v fccm, mpct, msel, fset, vsel_ input floating voltage input impedance > 1m 1.85 2.00 2.15 v fccm, mpct, msel, fset, vsel_ input high threshold 2.2 2.50 2.8 v
isl95210 6 fn6938.2 june 2, 2011 reference and dac system accuracy isl95210hrz -10c to +100c v out = {0.700v to 2.1625v}, v in = 5v -0.60 0.60 % v out = {0.48125v to 0.700v}, v in = 5v -0.75 0.75 % system accuracy isl95210irz -40c to +100c v out = {0.700v to 2.1625v}, v in = 5v -0.75 0.75 % v out = {0.48125v to 0.700v}, v in = 5v -1 1 % line regulation accuracy 4.5v < v in < 5.5v 0.05 % load regulation accuracy fccm = high, inductor dcr = 2m 0.08 % soft-start ramp soft-start and vsel slew rate 1.6 2.3 3.0 mv/s protection overcurrent trip level valley cu rrent limit (8 pwm pulse count) 10 12.5 14 a peak way-overcurrent (~1s delay) 28 35 43 a undervoltage threshold v out :v dac 81 84 87 % overvoltage rising threshold v out :v dac 112 116 120 % overvoltage falling threshold v out :v dac 99 102 106 % power-good pull-up resistance 1.8 2.3 2.8 k power-good pull-down resistance 30 50 70 v out soft-discharge resistance all shutdown conditions 25 45 65 power mosfet on-resistance high-side pmos +25c only - - 16.52 m high-side pmos - 14.8 19.5 m low-side nmos +25c only - -4.28m low-side nmos - 3.8 5.7 m over-temperature shutdown (note 6) thermal shutdown setpoint 150 c thermal recovery setpoint 125 c notes: 6. thermal impedance measured in still air on the isl952 10eval1z rev b evaluation board with 800khz setup. see an1485 . 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications recommended operating conditions , unless otherwise specified. boldface limits apply over the operating temperature range (-10c to +100c for isl95210hrz; -40c to +100c for isl95210irz). (continued) parameter test conditions min (note 7) typ max (note 7) units
isl95210 7 fn6938.2 june 2, 2011 typical performance curves figure 3. 800khz efficiency fccm = low figure 4. 800khz efficiency fccm = float figure 5. 800khz efficiency fccm = high figure 6. normal start-up figure 7. pre-biased start-up figure 8. ccm output voltage load regulation 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.00 10.00 i out (a) efficiency (%) 0.60 0.75 0.90 1.00 1.05 1.10 1.20 1.50 1.80 v out (v) 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.00 10.00 efficiency (%) i out (a) 0.60 0.75 0.90 1.00 1.05 1.10 1.20 1.50 1.80 v out (v) 50 55 60 65 70 75 80 85 90 95 100 012345678910 efficiency (%) i out (a) 0.60 0.75 0.90 1.00 1.05 1.10 1.20 1.50 1.80 vout (v) pg_out 5v/div en 5v/div i in 200ma/div v out 0.5v/div 0.1ms/div pg_out 5v/div en 5v/div i in 200ma/div v out 0.5v/div 0.1ms/div -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.01 0.10 1.00 10.00 accuracy (%) i out (a) v out = 1.10v high v out ripple with high esr high v out ripple with low esr low v out ripple
isl95210 8 fn6938.2 june 2, 2011 figure 9. output voltage load regulation (log scale) figure 10. ccm steady-state figure 11. audio mode steady-state figu re 12. audio mode steady-state (zoom) figure 13. dcm steady-state (100ma) figure 14. 10a load transient 50a/s typical performance curves (continued) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0.01 0.10 1.00 10.00 accuracy (%) i out (a) v out = 1.10v audio dcm audio dcm high v out ripple with low esr high v out ripple with high esr phase 2v/div v out (ac) 20mv/div 1s/div phase 2v/div v out (ac) 20mv/div 20s/div phase 2v/div v out (ac) 20mv/div 1s/div phase 2v/div 20mv/div 10s/div v out (ac) i out 5a/div 100mv/div 5s/div v out (ac)
isl95210 9 fn6938.2 june 2, 2011 figure 15. 10a load transien t 50a/s (zoom rising edge) figure 16. 10a load transien t 50a/s (zoom falling edge) figure 17. 10a load transient 5a/s fig ure 18. vsel1 transitions 0.90v to 1.80v figure 19. normal shut-down figure 20. overvoltage shut-down (vdac = 1.00v) typical performance curves (continued) i out 5a/div 50mv/div phase 5v/div 1s/div v out (ac) i out 5a/div v out 50mv/div phase 5v/div 2s/div i out 5a/div 100mv/div v out (ac) 5s/div 0.2ms/div vsel1 2v/div v out 500mv/div pg_out 5v/div en 5v/div v out 0.5v/div 5ms/div pg_out 5v/div v out 200mv/div 10s/div phase 2v/div
isl95210 10 fn6938.2 june 2, 2011 figure 21. undervoltage shut-down (vdac = 1.00v) figure 22. overcurrent shutdown figure 23. current derating over-temperature figure 24. current derating over-temperature (zoom) note: figures 23 and 24 were generated on the ISL95210EVAL1Z rev b evaluation board (4-layers/2oz. copper). the test conditions were 5v in and 1.8v out . the junction temperature was characterized by measuring the shif t over temperature of an integrated polysilicon resistor. for more details on the layer stack up of the evaluation board, please see the isl95210 application note ( an1485 ). typical performance curves (continued) pg_out 5v/div v out 200mv/div 10s/div phase 2v/div phase 5v/div pg_out 5v/div il 5a/div 0 2 4 6 8 10 12 25 50 75 100 125 ambient temperature (c) maximum continuous 85 output current (a) 200 lfm 100 lfm 300 lfm air flow 0 lfm 0 2 4 6 8 10 12 85 90 95 100 105 110 115 120 125 ambient temperature (c) maximum continuous output current (a) 200 lfm 100 lfm 300 lfm air flow 0 lfm
isl95210 11 fn6938.2 june 2, 2011 theory of operation the following sections will provide a detailed description of the inner workings of the isl95210 10a integrated fet regulator. start -up the isl95210 will not respond to any logic inputs until vcc and pvcc are above the power-on reset (por) level as described in the ?electrical specifications? table on page 5. once the por condition is achieved, the isl95210 will then acknowledge the states of its logic inputs. if the en pin is pulled above the rising threshold, the regulator is co mmanded on and the soft-start sequence is initiated. during soft-start, the programmed output voltage set point is determined by the logic states of vsel0, vsel1, mpct and msel. the output then ramps digitally to the regulation voltage in 2.5mv/s steps. once the output voltage achieves regulation, the power-good monitor output (pg_out) is toggled high to the voltage provided on the pg_in pin. figure 25 illustrates the ideal soft-start behavior. using the values in tables 1 and 2, the soft-start interval can be easily calculated by equation 1. the units of equation 1 are in microseconds. for example: -v dac = 1.200v -t ss = 1.200v / 0.0025 = 480s the fixed soft-start slew rate of 2.5mv/s allows for easy calculation of the in-rush current. consequently, the in-rush is manageable for all practical values of output capacitance. for example: -c out = 330f -i inrush = 2500*330f = 0.825a output voltage programming the highly integrated nature of the isl95210 simplifies design and reduces component count. the vsel0 and vsel1 pins are 3-state logic inputs to an integrated dac that controls the output voltage set point as prescribed in table 1. this allows the user to progra m the output voltage without the use of a resistor divider network. however, if the user wishes to program values of v out away from the dac values, a resistor divider can be used. because the input impedance of the vout pin is relatively low, the top resistor in the divider stack (r1 in figure 31) must be kept small to minimize regulation error as the internal resistance changes over-temperature and process tolerances. a 100 resistor is an ideal choice. the bottom resistor in the divider stack (r2 in figure 31) can be derived from equation 3: for example: -v dac = 1.200v - desired v out = 1.220v -r1 = 100 - r2 = 5.885k the use of a resistor network also limits the soft discharge feature of the isl95210. more detail on this operation can be found in the ?soft-discharge? on page 14. in addition to digitally controlled output voltage programming, the isl95210 includes the ability to margin the output voltage up and down from the set point for use in end-of-line manufacturing reliability tests. the mpct pin controls the amount of margining desired by the user and the msel pin determines when margining is engaged. in all margining conditions, the output voltage is slewed to the new value at the soft-start rate of 2.5mv/s. table 2 shows the output voltage as dictated by mpct and msel. figure 25. idealized soft-start waveform pg_out en vout 1us 2.5mv dac voltage t ss en dac voltage vout 2.5mv 1s t ss pg_out t ss v dac 0.0025 ------------------ - = (eq. 1) i inrush 2500 c out ? () = (eq. 2) table 1. dac controlled output voltage settings vsel1 vsel0 v out (v) 0 0 0.600 0 f 0.750 0 1 0.900 f 0 1.000 f f 1.050 f1 1.100 1 0 1.200 1 f 1.500 1 1 1.800 r2 r1 v dac ? v out 2r1 ? 205k --------------- ?? ?? 205k r 1 + 205k --------------------------- ?? ?? ? + v dac ? -------------------------------------------------------------------------------------------------- - = (eq. 3)
isl95210 12 fn6938.2 june 2, 2011 each of the margin targets represents the dac code nearest to the desired value. table 3 shows the actual targets for each margin setting (see table 4 on page 16 for the full output truth table). both the dac and margining features can be used ?on the fly?, meaning the voltage can be chan ged during normal operation. regulation r4 modulator the r 4 modulator is an evolutionary step in r 3 technology. like r 3 , the r 4 modulator allows variable frequency in response to load transients and maintains the benefits of current-mode hysteretic controllers. however, in addition, the r 4 modulator reduces regulator output impedance and uses accurate referencing to eliminate the need for a high-gain voltage amplifier. the result is a topology that can be tuned to voltage-mode hysteretic transient speed while maintaining a linear control model and removes the need for any compensation. this greatly simplifies the regulator design for customers and reduces external component count and cost. stability the removal of compensation derives from the r 4 modulator?s lack of need for high dc gain. in traditional architectures, high dc gain is achieved with an integrator in the voltage loop. the integrator introduces a pole in th e open-loop transfer function at low frequencies. that, combined with the double-pole from the output l/c filter, creates a thre e pole system that must be compensated to maintain stability. classic control theory requires a single-pole tran sition through unity gain to ensure a stable sy stem. current-mode architectures (includes peak, peak-through , current-mode hysteretic, r 3 and r 4 ) generate a zero at or near th e l/c resonant point, effectively canceling one of the system?s po les. the system still contains two poles, one of which must be canceled with a zero before unity gain crossover to achieve stability. compensation components are added to introduce the necessary zero. figure 26 illustrates the classic integrator configuration for a voltage loop error-amplifier. while the integrator provides the high dc gain required for accurate regulation in traditional technologies, it also introduces a low-frequency pole into the control loop. figure 27 shows the open-loop response that results from the addition of an integrating capacitor in the voltage loop. the compensation components found in figure 26 are necessary to achieve stability. table 2. output voltage margining control msel mpct result 0 0 no margining 0 f no margining 0 1 no margining f 0 margin down dac - 15% ffmargin down dac - 10% f 1 margin down dac - 20% 1 0 margin up dac + 15% 1 f margin up dac + 10% 1 1 margin up dac + 20% table 3. output voltage margin targets vout -20% -15% -10% +10% +15% +20% 0.600 0.481 0.513 0.538 0.663 0.688 0.719 0.750 0.600 0.638 0.675 0.825 0.863 0.900 0.900 0.719 0.763 0.813 0.988 1.038 1.081 1.000 0.800 0.850 0.900 1.100 1.150 1.200 1.050 0.838 0.894 0.944 1.156 1.206 1.263 1.100 0.881 0.938 0.988 1.213 1.263 1.325 1.200 0.963 1.019 1.081 1.319 1.381 1.438 1.500 1.200 1.275 1.350 1.650 1.7250 1.800 1.800 1.438 1.531 1.619 1.981 2.069 2.163 figure 26. integrator error-amplifier configuration v out v dac v comp integrator for high dc gain compensation for/to counter integrator pole figure 27. uncompensated integrator open-loop respons e p1 p2 p3 l/c double-pole integrator pole z1 current- mode zero - 6 0 d b / d e c - 2 0 d b / d e c -20db crossover required for stability compensator to add z2 is needed - 4 0 d b / d e c traditional loop gain (db)
isl95210 13 fn6938.2 june 2, 2011 because r 4 does not require a high-gain voltage loop, the integrator can be removed, reducing the number of inherent poles in the loop to two. the current-mode zero continues to cancel one of the poles, ensuri ng a single-pole crossover for a wide range of output filter choice s. the result is a stable system with no need for compensation components or complex equations to properly tune the stability. figure 28 shows the r 4 error-amplifier that does not require an integrator for high dc gain to achieve accurate regulation. the result to the open loop respon se can be seen in figure 29. transient response in addition to requiring a compen sation zero, the integrator in traditional architectures also slow s system response to transient conditions. the change in comp vo ltage is slow in response to a rapid change in output voltage. if the integrating capacitor is removed, comp moves as quickly as v out , and the modulator immediately increase s or decreases switching frequency to recover the output voltage. the dotted red and blue lines in figure 30 represent the time delayed behavior of v out and v comp in response to a load transient when an integrator is used. the solid red and blue lines illustrate the increased response of r 4 in the absence of the integrator capacitor. discontinuous conduction modes the isl95210 supports two powe r saving modes of operation during light load conditions. if fccm is asserted high, the regulator remains in continuous conduction mode (ccm) which offers the best transient response and the most stable operating frequency. if the fccm pin is pulled to ground potential, the regulator will operate in full discontinuous conduction mode (dcm). in this mode, the inductor current is monitored and prohibited from going negative. when the inductor current reaches zero, both internal power mosfets are turned off. the output voltage then decays solely as a function of load. the power fets remain off until the output voltage droops enough to trigger a pwm on pulse. because the rate of decay of v out scales proportionally with load, so does the switch ing frequency. this increases efficiency as the relatively fixed power loss associated with switching the power fets is averaged over the switching period. if the fccm pin is left floating, the isl95210 will operate in audio mode dcm. this mode operates largely the same as full dcm mode with one exception; the switching period is monitored cycle by cycle. if the load diminishes to a point where the switching frequency begins to drop below ~28khz, the isl95210 control loop will issue a pwm on pulse to ensure the frequency remains above the upper threshold for human hearing. this allows flexibility for designs that are sensitive to audio frequency interference. like r 3 , the r 4 architecture seamlessly enters and exits all power saving modes to ensu re accurate regulation. protection and shutdown features the isl95210 offers a full suite of protection features to reduce the risk of damage to the ic and load. they include under and overvoltage monitoring and prot ection as well as protection against excessive current and thermal operating conditions. figure 28. non-integrated r4 error-amplifier configuration r1 r2 v out v dac v comp f (hz) p1 p2 l/c double-pole z1 current- mode zero - 2 0 d b / d e c system has 2 poles and 1 zero no compensator is needed - 4 0 d b / d e c r4 loop gain (db) - 2 0 d b /d e c figure 29. uncompensated r4 open-loop response figure 30. r3 vs r4 idealized transient response r3 t r4 v out v comp i out
isl95210 14 fn6938.2 june 2, 2011 undervoltage protection if the output voltage dips too lo w during normal operation, the isl95210 recognizes a fault condition and shuts down. when v out goes 16% below v dac , the power-good monitor flags pg_out low and tri-states the phase node by turning off both integrated power mosfets. in addition, the soft-discharge mosfet is turned on to gently pull the output voltage to ground potential for the next restart. the undervoltage fault remains latched until a por event or en is toggled. overvoltage protection during normal operation, the outp ut voltage is monitored at all times to ensure it does not exceed the set point by more than 16%. excessively high voltages can cause failure to output capacitors as well as the load. if v out goes above 116% of dac, the power-good monitor is flagged by toggling pg_out low and the ic enters overvoltage protection mode. in overvoltage protection mode, the upper p-channel mosfet is latched off until the fault is cleared. in addition, v out is compared against the reference dac voltage. if v out is above dac, the lower n-channel mosfet is turned on to pull v out down. if v out falls below dac, the lower n-channel mosfet is turned off. this process repeats until the fault condition is cleared through vcc/pvcc por or a recycling of the en pin. this produces a soft-crowbar action that can effectively pull the output away from dangerously high voltage levels without causing the negative voltage swings on vout that are present with full crowbar implementations of overvoltage protection. overcurrent protection if the current draw from the load becomes too high during operation, the ic protects itself and the load by latching off. the overcurrent mechanism is implemented as a two-fold protection scheme. the isl95210 continuously monitors the lower n-channel mosfet current. it stores the vall ey of the inductor current each cycle and compares it against th e lower overcurrent protection (ocp) threshold of 11a nominall y. if the ocp threshold is achieved for 8 consecutive pwm cycles, an overcurrent fault is detected and the ic is shutdown. in this event, power-good monitor flags pg_out low and tr i-states both switching power mosfets and turns on the soft-discharge fet. inductor valley current is used to ensure that the minimum ocp threshold is above the maximum isl95210?s normal maximum load of 10a regardless of chosen inductor value. in addition to valley current limit, the upper p-channel mosfet current is continuously monitored. if a catastrophic overcurrent event is encountered (e.g. short circuit on v out ), the isl95210 immediately responds to protect the output by latching both mosfets off and engaging the soft-discharge fet. the power-good monitor flags pg_out low and the ic remains latched off until por or en is toggled. thermal protection the isl95210 actively monitors the die temperature to protect against harmful thermal operatin g conditions. if the silicon temperature exceeds +150c, the controller will suspend operation and shut down until th e ic junction temperature falls below +135c. once the temperature has fallen below the lower protection threshold, the ic will resume normal operation following a por event or toggling of the en input. power-good monitor a status indicator is provided to inform the system whether or not the isl95210 output voltage is in regulation or if a fault has occurred. if vcc and pvcc are abov e the por threshold, the part is enabled, and no faults have been detected, pg_out will toggle high. the power-good monitor is a cmos configuration (refer to the ?functional block diagram? on page 2). this allows the user to provide any voltage to indicate when power is good. the voltage provided on to the pg_in pin will be used as the logic high value for pg_out. this has the advantage over open-drain configurations of saving a pull-up resistor. a pull-up resistor on pg_out can still be used if desired. in this configuration, the pg_in pin needs to be floated. soft-discharge to ensure a known operating condition when the isl95210 is in a standby state, the vout pin is actively discharged to pgnd through an integrated 45 mosfet. the mosfet is commanded on if the en pin is pulled low or if any of the previously mentioned fault conditions are achieved with the exception of overvoltage, which actively pulls down on v out as a matter of protection. it should be noted that if an external resistor divider is used to program v out to values not found in the dac table, the soft-discharge feature will be negatively impacted. figure 31 illustrates this condition. the discharge resistance is increased by the presence of the resistor divider. the total discha rge resistance is expressed in equation 4: figure 31. simplified soft-discharge circuit v out soft-discharge vout r1 r2 isl95210 45 r dchrg 45 ii r2 () r1 + = ? (eq. 4)
isl95210 15 fn6938.2 june 2, 2011 general application design guide this design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase power converter. it is assumed that the reader is familia r with many of the basic skills and techniques referenced in the fo llowing section. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts. selecting the lc output filter the duty cycle of an ideal buck converter is a function of the input and the output voltage. this relationship is written as equation 5: the output inductor peak-to-peak ripple current is written as equation 6: a typical step-down dc/dc converter will have an i p-p of 20% to 40% of the maximum dc output load current. the value of i p-p is selected based upon several criteria such as mosfet switching loss, inductor core loss, and th e resistive loss of the inductor winding. the dc copper loss of th e inductor can be estimated by equation 7: where i load is the converter output dc current. the copper loss can be significant so attention has to be given to the dcr selection. another factor to consider when choosing the inductor is its saturation characte ristics at elevated temperature. a saturated inductor could cause destruction of circuit components, as well as nuisance ocp faults. a dc/dc buck regulator must have output capacitance c o into which ripple current i p-p can flow. current i p-p develops a corresponding ripple voltage v p-p across c o, which is the sum of the voltage drop across the capacitor esr and of the voltage change stemming from charge moved in and out of the capacitor. these two voltages are written as equation 8: and equation 9: if the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total esr until the required v p-p is achieved. the inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. low inductance capacitors should be considered in this scenario. a capacitor dissipates heat as a function of rms current and frequency. be sure that i p-p is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated rms current at f sw . take into account that the rated value of a capacitor can fade as much as 50% as the dc voltage across it increases. selection of the input capacitor the important parameters for the bulk input capacitance are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the rms current required by the switching circuit. their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a preferred rating. figure 32 is a graph of the input rms ri pple current, normalized relative to output load current, as a function of duty cycle and is adjusted for a converter efficiency of 80%. the ripple current calculation is written as equation 10: where: - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of i max (0% to 100%) - d is the duty cycle that is adjusted to take into account the efficiency of the converter, which is written as equation 11: in addition to the bulk capacitance, some low esl ceramic capacitance is recommended to decouple between the drain of the high-side mosfet and the source of the low-side mosfet. layout considerations it is important to place power co mponents as close as possible to the devices they decouple. figure 33 provides an example of proper power component placement for the isl95210. the colored shapes represent the following power planes: d v o v in -------- = (eq. 5) (eq. 6) i pp v o 1d ? () ? f sw l ? ---------------------------- = (eq. 7) p copper i load 2 dcr ? = v esr i p-p e ? sr = (eq. 8) v c i p-p 8c o f ? sw ? --------------------------- = (eq. 9) pgnd phase vin vout (eq. 10) i in_rms normalized , dd 2 ? () d x 2 12 ------ - ? ?? ?? + = d v o v in eff ? ---------------------- - = (eq. 11) figure 32. normalized rms input current 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 normalized input duty cycle rms ripple current x = 1 x = 0.75 x = 0.50 x = 0.25 x = 0
isl95210 16 fn6938.2 june 2, 2011 input capacitors are placed directly across vin and pgnd to filter switching currents between the pmos and nmos power fets. the output inductor is placed directly adjacent to the phase pins. its ?north-south? arrangements easily allow for the output voltage decoupling capacitor to be placed with its ground terminal very near the input capacitors grounds and the pgnd pins of the isl95210. this provides a low impedance return path for the inductor ripple current. this is one possible arrangement that will result in a good layout. the analog ground connection (not shown) should be connected directly to the ground plane th rough a via. the vcc decoupling capacitor should be placed next to the vcc and agnd pins for optimal noise rejection. copper size for the phase node the parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. it is best to limit the size of the phase node copper in strict accordance with the current and thermal management of the application. an mlcc should be connected directly between vin and pgnd to suppress the turn-off voltage spike. this is achieved by placing the mlcc as close to the ic as possible and adjacent to vin and pgnd. table 4. output voltage truth table msel mpct vsel1 vsel0 vout f 1 0 0 0.48125 f 0 0 0 0.51250 f f 0 0 0.53750 00000.60000 0 f 0 0 0.60000 01000.60000 f 1 0 f 0.60000 f 0 0 f 0.63750 1 f 0 0 0.66250 figure 33. isl95210 power component layout example f f 0 f 0.67500 10000.68750 f1010.71875 11000.71875 0 0 0 f 0.75000 0f0f0.75000 0 1 0 f 0.75000 f0010.76250 f1f00.80000 ff010.81250 1f0f0.82500 f 1 f f 0.83750 f0f00.85000 1 0 0 f 0.86250 f1f10.88125 f 0 f f 0.89375 00010.90000 0 f 0 1 0.90000 01010.90000 f f f 0 0.90000 1 1 0 f 0.90000 f0f10.93750 ffff0.94375 f 1 1 0 0.96250 fff10.98750 1 f 0 1 0.98750 0 0 f 0 1.00000 0 f f 0 1.00000 0 1 f 0 1.00000 f0101.01875 10011.03750 0 0 f f 1.05000 0 f f f 1.05000 0 1 f f 1.05000 ff101.08125 11011.08125 00f11.10000 0ff11.10000 01f11.10000 1ff01.10000 1 0 f 0 1.15000 1 f f f 1.15625 table 4. output voltage truth table (continued) msel mpct vsel1 vsel0 vout
isl95210 17 fn6938.2 june 2, 2011 00101.20000 0 f 1 0 1.20000 01101.20000 f 1 1 f 1.20000 1 1 f 0 1.20000 1 0 f f 1.20625 1ff11.21250 1 0 f 1 1.26250 1 1 f f 1.26250 f01f1.27500 1f101.31875 1 1 f 1 1.32500 f f 1 f 1.35000 10101.38125 f1111.43750 11101.43750 0 0 1 f 1.50000 0f1f1.50000 0 1 1 f 1.50000 f0111.53125 ff111.61875 1f1f1.65000 1 0 1 f 1.72500 00111.80000 0 f 1 1 1.80000 01111.80000 1 1 1 f 1.80000 1f111.98125 10112.06875 11112.16250 table 4. output voltage truth table (continued) msel mpct vsel1 vsel0 vout
isl95210 18 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6938.2 june 2, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl95210 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 5/18/11 fn6938.2 added ?32 lead, 6mmx4mm qfn package? to ?features? on page 1. 5/10/11 fn6938.1 initial release to web.
isl95210 19 fn6938.2 june 2, 2011 package outline drawing l32.6x4b 32 lead quad flat no-lead plastic package rev 0, 09/08 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 110 11 16 17 26 27 32 2x 6.00 pin 1 index area 4.00 b a 0.10 c 0 . 2 ref 0-0.05 5 see detail "x" 0.10 max. 1.00 c c seating plane 0.08 c 16 (11x 0.50) 6.40 (14x 0.25) package boundary (11x 0.45) 3x 0.95 (4.40) (1.80) (2.5) (2x 4.7) (2x 1.12) 18x 0.55 (2.64) (18x 0.25) (14x 0.50) 18x 0.55 2x 1.12 0.50 11x 14x 0.25 2x 4.70 chamfer 0.300 x45 pin #1 identification 11x 0.25 1.80 3x 0.75 2.50 2x 2.64 (2.50) 0.50 14x 18x 0.35 18x 0.25 b mc 0.10 a 4 m 4 0.10 c a b

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